Attention has lately been focused on a system-in-package technology whereby a plurality of semiconductor chips each provided with an IC are mounted at a high density, thereby implementing a high-performance system in a short period of time, and a variety of mounting structures have since been proposed by various companies. Vigorous progress has been made in development of a stacking package capable of achieving significant reduction in size by three-dimensionally stacking a plurality of semiconductor chips, in particular.
As disclosed in, for example, Patent Document 1, because wire bonding is mainly used for electrical connection between three-dimensionally stacked semiconductor chips and a mount substrate, respectively, an upper tier chip of the stacked semiconductor chips needs to be smaller in size than a lower tier chip thereof, so that in the case of stacking semiconductor chips identical in size to each other, it becomes necessary to secure a wire bonding area by adopting a structure where a spacer is sandwiched between the respective semiconductor chips. Such electrical connection by use of the wire bonding as described has high flexibility in routing of wiring, and is therefore a very effective method for implementing electrical connection among a plurality of existing semiconductor chips with short TAT (Turn Around Time), and at a low cost.
With the electrical connection by the wire bonding, however, every metal interconnect from the plurality of the chips needs to be once dropped on the mount substrate before re-routing the same to the other chips, so that this has caused a problem that respective lengths of the metal interconnects between the respective chips become very long, and another problem that a metal interconnect density of the mount substrate becomes very high. Accordingly, this has raised a possibility of causing a problem that a production yield deteriorates owing to a higher metal interconnect density on the mount substrate to thereby cause an increase in the cost of the substrate in addition to a problem of an increase in inductance between the chips, resulting in difficulty with fast transmission. In Patent Documents 2, and 3, there has been proposed a method whereby electrodes penetrating through the interiors of the respective chips are formed for use in connection between the upper and lower chips to counter those problems associated with the electrical connection by the wire bonding. In Patent Document 2, penetration electrodes are formed concurrently with the process step of manufacturing a device comprising, for example, copper metal interconnects, thereby providing semiconductor chips with the penetration electrodes, having achieved significant simplification in manufacturing steps. In Patent Document 3, there is provided a method whereby electrodes with solder or a low-melting metal, embedded in through-holes formed in the chip by employing an electrolytic plating or electroless plating method, are formed above or below respective chips and the chips are stacked one on top of another before applying heat, thereby effecting three-dimensional connection between the chips through melt-bonding.
Patent Document 1
    Japanese Patent Laid-open H 11 (1999)-204720Patent Document 2    Japanese Patent Laid-open H 11 (1999)-251316Patent Document 3    Japanese Patent Laid-open 2000-260934
As described above, the method of using the wire bonding is in the mainstream of the methods of packaging a plurality of semiconductor chips by three-dimensionally stacking the same, however, looking ahead, it is anticipated that the respective lengths of metal interconnects will become a bottleneck against fast transmission, and securing of wire bonding areas also will become a bottleneck against reduction in size and thickness. Further, the flip chip bonding whereby metal bumps are directly connected to electrodes on a mount substrate, respectively, has been in widespread use, however, taking into account advances being made in increase of the number of connection pins of an LSI chip, and in finer connection pitches thereof, a possibility exists that misalignment occurs between electrodes on respective chips, and the electrodes on the mount substrate, owing to, for example, a difference in thermal expansion between constituent materials, resulting in failure of bonding. Most of conventional bonding technologies are basically methods for bonding by utilizing thermal energy, including a method for causing melt-bonding of metal by heating a metal-bonding material, such as solder and so forth, in the air, a method for bonding by applying energy such as ultrasonic waves, and so forth. Accordingly, in order to implement microscopic bonding from now on, a bonding technology capable of reduction in bonding temperature, and reduction in load is indispensable.
A method for implementing three-dimensional connection between chips with the shortest metal interconnect length, using penetration electrodes, has been proposed, but since a process for forming the penetration electrodes is a novel process not included in the conventional wafer process and mounting process, it is required as preconditions for introduction of such a process that a process load is small, TAT (Turn Around Time) is short, a method for implementing connection is easy to execute, and reliability as good as in the conventional case can be ensured. For example, with the method for forming bump electrodes by causing growth of solder plating in the through-holes formed in the chip as disclosed in Patent Document 3, problems are encountered in that it normally takes a fair amount of time (several hours or more) for the growth of the solder plating, and it is technically difficult to uniformly cause the growth of the solder plating in the through-holes high in aspect ratio. Further, no sufficient mention has been made of how the semiconductor chips as finally stacked are to be connected to, for example, an organic mount substrate largely differing in coefficient of linear thermal expansion.
In view of the problems described as above, it is an object of the invention to provide a method of manufacturing a semiconductor device, capable of electrical connection between stacked chips, and between stacked chips and a metal interconnect substrate at a low cost and short TAT while using a low-temperature process at an ordinary temperature level.